For example, as shown in FIG. 11, a conventional semiconductor device has a stacked via structure, whereby an electrode pad 22 serving as an electrode for external connection has a first pad metal 67 formed in the top layer and a second pad metal 65 formed in a wiring layer immediately under the first pad metal 67. The first pad metal 67 and the second pad metal 65 are electrically connected to each other through vias 66. The stacked via structure is connected to wiring 10 and so on via a stacked structure of a drawing metal 81. The wiring 10 is formed in an area other than an area immediately below the electrode pad 22 and is connected to a circuit element on a semiconductor substrate.
Another structure is proposed in which a pad for external connection is disposed on an element formation area of an input/output circuit cell to reduce a chip size. For example, a semiconductor integrated circuit is proposed in which an interlayer insulating film is disposed on a logic circuit and a driver circuit and an input or output pad is formed thereon (See Japanese Patent Laid-Open No. 06-244235).
However, when an electrode pad is formed on an element, the wiring and the interlayer insulating film immediately under the pad may be damaged by an impact load during wire bonding and so on. Alternatively, a diffusing element formed immediately under the pad, e.g., a transistor may change (degrade) its performance characteristics.
Particularly in wire bonding using a gold ball bond, a semiconductor chip is heated to 230 to 240° C. and an ultrasonic wave is applied while a predetermined load is applied, so that an oxide film on a surface of an aluminum pad is broken and a gold-aluminum alloy is formed on the intrinsic surface of aluminum and the interface of gold. Thus, a crack appears on the interlayer insulating film (made of SiO2 or the like) due to stress caused by ultrasonic energy on the interface between metal and the interlayer insulating film under the pad.
Also in a wafer test by the cantilever method which is an ordinary method for a wafer test, an electrode pad is pressed by a probe needle made of tungsten or the like. Thus, a highly concentrated load is applied immediately below the electrode pad and a crack appears on the interlayer insulating film. Further, the electrode pad has a needle mark (indentation) of the probe needle. In the indentation, aluminum on a surface of the pad is scraped off by the probe needle and thus an alloy of a gold ball is not formed during wire bonding on the electrode pad after the wafer test. In recent years, a smaller bonding pitch is demanded for wire bonding and a pad size and a ball diameter have decreased. Thus, an area of an indentation has increased relatively, and the formation of an alloy or bonding cannot be performed in a predetermined area.
FIG. 12 is a distribution chart showing stress occurring on the interlayer insulating film when ball bonding is performed on the electrode pad under which wiring section is disposed. FIG. 12 shows a result of calculating a stress distribution according to CAE analysis (finite element method) when a metal bump is formed on a four-layered wiring structure by gold ball bonding.
Under a pad metal 61 (hereinafter, referred to as a first metal 61) in the top layer, a first interlayer insulating film 71 and a pad metal 62 (hereinafter, referred to as a second metal 62) in the second layer are formed. Under the second metal 62, a second interlayer insulating film 72, a third metal 91, a third interlayer insulating film 73, and a bottom layer metal 10 are formed. When an ultrasonic wave is applied along an arrow of FIG. 12 to form a metal bump 43 on the first metal 61, stress is concentrated on edges of the lower metals 62 and 91 (illustrated as whitish portions in FIG. 12).
When the stress exceeds the yield stresses of the interlayer insulating films 71, 72, and 73, a brittle fracture occurs and a crack appears. The CAE analysis proves that internal stress also increases according to the magnitude of applied ultrasonic energy. Moreover, it is found that a transistor formed immediately below the bonded electrode pad degrades its characteristics (Vt, Gm, hot carrier life time, etc.).
The present invention is devised to solve these problems. It is an object of the present invention to reduce damage on a surface of an electrode pad, a lower wiring, and an interlayer insulating film during bonding and probing.